1. Technical Field
The present invention relates in general to a method and system for using constraints to simplify a memory controller. More particularly, the present invention relates to a method and system for simplifying a memory controller design by following constraints that reduce/eliminate command collisions, data conflicts, and/or the need to check particular timing parameters in a memory system.
2. Description of the Related Art
Computer system developers constantly strive to increase a computer system's performance. The developers may focus on optimizing software components and/or hardware components in order to achieve this goal. One hardware optimization approach is to improve a processor's rate of reading from memory and writing to memory.
Hardware developers have designed a dynamic random access memory (DRAM) interface that includes a high-speed chip-to-chip data transfer technology. The interface technology may be implemented on standard CMOS DRAM cores and CMOS controller chips for applications such as high-performance main memory, PC graphics, game consoles, advanced digital consumer systems, high-performance networking systems, and other demanding applications requiring high-bandwidth memory subsystems. A memory system that incorporates the newly developed DRAM interface includes a memory controller that issues commands on a command bus to the DRAM through an input/output interface. These commands correspond to read and write operations whereby a typical command sequence for either operation would be an “Activate” command, one or more “Column” commands, and a “Precharge” command. The activate command, also referred to as a row command, opens or senses a row or a page. The column command reads to or writes from a column within a row or page. And finally, the precharge command closes a row or a page.
A memory controller designer factors in many device (i.e. DRAM) timing parameters and their ranges of value when designing a memory controller. Invariably, the memory controller designer identifies many parameter value combinations that would cause command collisions, data conflicts, or the need to check particular timing parameters. For example, the memory controller designer is required to design a memory controller such that the memory controller issues commands that correspond to a read operation far enough away from commands that correspond to a write operation, and in such a way that the commands do not collide despite the fact that there is usually some operation duration overlap.
A challenge found with designing a memory controller is resolving troublesome parameter value combinations without overly designing the memory controller. The memory controller may become very complicated, and potentially not function correctly and/or miss schedule milestones, if it includes mechanisms to handle each and every such parameter value combination.
What is needed, therefore, is a method and system to simplify a memory controller design, while maximizing memory controller performance and maintaining support for wide ranges of parameter values.